1. Field of the Invention
This invention relates to a clock signal distribution circuit that can distribute a high frequency clock signal to a plurality of registers.
2. Description of the Related Art
To distribute a high frequency clock signal, the reduction of clock skew and the increase of a driving capability have previously been attempted. Several methods of clock distribution have been known, such as follows:
The first example is a tree structure driving method represented by an H-Tree structure (for example, as disclosed in "IEEE 1992 CUSTOM INTEGRATED CIRCUITS CONFERENCE", 28.3.1-28.3.4) in which it is possible to achieve a reduced clock skew by equalization of loads and an increased driving capability by a hierarchical arrangement of buffers.
The second example is a large driver packaged driving method (for example, as disclosed in "IEEE 1992 INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE", TA 6.2, pp. 106-107) in which it is possible to achieve the reduced skew by reducing a wire delay time by means of a low resistance clock trunk line design, and to increase a driving capability by means of a large driver. An inverter having a simple structure and a large driving capability is utilized as a buffer of the tree structure driving method. To attain a large driving capability, the size of an inverter is increased, and the number of branches in the tree structure is reduced. A hierarchical structure made up of a number of inverters is utilized as a driver of the large driver packaged driving method.
Moreover, as the third example of techniques for reducing clock skew in the tree structure driving method, as disclosed in Japanese Patent Application Kokai Publication No. Hei-4(1992)-373160, short-circuiting of buffer output terminals at the final stage of a distribution circuit is also known. FIG. 1 shows such a conventional clock signal distribution circuit wherein the buffers of the final stage are mutually connected or short-circuited with each other. More specifically, this circuit is formed by a buffer 401 of a first stage, buffers 402-405 of a second stage, and buffers 411-414, 421-424, 431-434 and 441-444 of a third stage, and output terminals of all the third stage buffers 411-444 are short-circuited by a plurality of short-circuit wirings 471-494.
However, the above mentioned conventional clock signal distribution circuits according to these methods have the following drawbacks.
Specifically, it is, in principle, impossible for the large driver packaged driving method to realize zero skew because there is a difference in distance from a driver to each register. On the other hand, it is theoretically possible for the tree structure driving method to realize zero skew by making a design in such a way that a buffer load of each stage is perfectly equalized. However, in effect, it is difficult for this method to realize zero skew because of changes in parasitic components of a clock signal line and changes in a buffer driving capability due to various restrictions on a clock signal wiring design (such as an area and a design period) and process variations. In the case of the reduction of skew by damping or canceling the generated skews by means of short-circuiting of buffer output terminals at the final stage of a distribution circuit in the tree structure driving method, the larger the skew caused before the final stage, the smaller the skew damping effect becomes, because of parasitic components of a short-circuit wire. In addition, when a large skew ranging to a half cycle of a clock signal is caused, a signal waveform is destroyed. Therefore, it is difficult to realize the reduction of skew which becomes more important when a clock frequency is increased.
The development of a microminiaturization technique and the extension of the length of a clock signal wire result in increased wire resistance, and this in turn deteriorates the sharpness of the rise and fall characteristics that are needed for distributing a high frequency clock signal. The maximum waveform sharpness effect will be reached even if a driving capability is increased by enlarging the size of a single inverter which acts as a buffer of the tree structure. Moreover, an increase in wire resistance as a result of microminiaturization results in the maximum waveform sharpness effect being reached earlier. Even when a driving capability is increased by the reduction of a load at each buffer stage which is achieved by reducing the number of branches in the tree structure, the number of buffers constituting the tree structure is increased. The buffers are arranged with allowance for equalization of loads, and hence the design of the clock signal distribution circuit becomes very complex. Also, it becomes more difficult to attain the equalization of loads.